Multiple Retest Systems for Screening High-Quality Chips

In this study, we develop a digital integrated circuit testing model (DITM) based on statistical simulation method to evaluate the test quality and yield of products. This can be used quantify characteristics device under (DUT) simulate effect guardband (TGB) results during testing. The complexity functionality circuits have continued increase over past two decades. Moreover, development in speed automated equipment (ATE), e.g., OTA or overall timing accuracy, according ITRS report, lags behind progress semiconductor manufacturing. Hence, using existing instruments tools select zero-defect products would considerable challenge for suppliers due slow technology. We propose new scheme multiple retest systems (MRSs) improve while maintaining desired address product requirements consumers. also use set parameters from IRDS 2021 (International Roadmap Devices Systems 2021) estimate future (Yt) through DITM calculations. MRS showed that improved achieving expected quality. MRSs not only performance tester but demonstrate effective improvement high-quality approach enables high-quality, high-yield chip delivery, significantly increases profit company.